In the fabrication of semiconductor components, metal conductor lines are formed over a substrate containing device circuitry. The metal conductor lines serve to interconnect discrete devices, and thus form integrated circuits. The metal conductor lines are further insulated from the next interconnection level by thin films of insulating material deposited by, for example, CVD (Chemical Vapor Deposition) of oxide or application of SOG (Spin On Glass) layers followed by fellow processes. Holes, or vias, formed through the insulating layers provide electrical connectivity between successive conductive interconnection layers. In such wiring processes, it is desirable that the insulating layers have a smooth surface topography, since it is difficult to lithographically image and pattern layers applied to rough surfaces.
Also, deep (greater than 3 .mu.m) and narrow (less than 2 .mu.m) trench structures have been used in advanced semiconductor design for three major purposes: (1) to prevent latchup and to isolate n-channel from p-channel devices in CMOS circuits; (2) to isolate the transistors of bipolar circuits; and (3) to serve as storage-capacitor structures in DRAMS. However in this technology it is even more crucial to precisely determine the endpoint of differing materials to prevent unnecessary dishing out of the connector metal.
Chemical-mechanical polishing (CMP) has been developed for providing smooth insulator topographies. CMP can also be used to remove different layers of material from the surface of a semiconductor wafer. For example, following via formation in a dielectric material layer, a metallization layer is blanket deposited and then CMP is used to produce planar metal studs. Briefly, the CMP processes involve holding and rotating a thin, flat semiconductor wafer against a wetted polishing surface under controlled chemical, pressure, and temperature conditions. A chemical slurry containing a polishing agent, such as alumina or silica, is used as the abrasive material. Additionally, the chemical slurry contains selected chemicals which etch or oxidize various surfaces of the wafer during processing. The combination of mechanical and chemical removal of material during polishing results in superior planarization of the polished surface. In this process it is important to remove a sufficient amount of material to provide a smooth surface, without removing an excessive amount of underlying materials. The accurate material removal is particularly important in today's submicron technologies where the layers between device and metal levels are constantly getting thinner. Therefore, a precise polishing endpoint detection technique is highly desirable.
In the past, endpoint has been detected by interrupting the CMP process, removing the wafer from the polishing apparatus, and physically examining the wafer surface by techniques which ascertain film thickness and/or surface topography. In these processes, if the wafer did not meet specifications, it was loaded back into the polishing apparatus for further planarization. If too much material was removed, the wafer was often substandard to the specifications or had to be discarded altogether. By experience, an elapsed CMP time has been developed with some accuracy for a given CMP process. However, this endpoint detection method is time consuming, unreliable, and costly.
Various active processes have been developed to circumvent the problems associated with this particular endpoint detection method. However, these active processes suffer from their own disadvantages and inaccuracies.
Accordingly, what is needed in the art is an improved passive method of more accurately determining the end point of one semiconductor wafer layer and the beginning of the next layer.